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flip flop shoe saleWQA http://www.farfield-group.com/Flip-Flop.asp Check for two

Pay attention to two negedges in always block
Instead, it shows in the event the register/latch per the block has to change states,
flip flop shoe sale, typically on a clock edge (register) or level change (latch).
If you are attempting to detect a good edge on an input, like for an interrupt detection, the recommended method is to synchronise the edge to an internal shift register.
So,
flip flop, for your application,
http://www.farfield-group.com/Flip-Flop.asp, you may want to do the above twice then make use of the two edge detect signals to control a few other device/block.
The magic formula to keep in mind with all HDL jobs are that HDL stands for Hardware Description Language. This is a replacement for schematics, not software. draw the schematic then write the HDL that describes that circuit schematic.
Whatever you wrote is perfectly valid Verilog,
cheap filp.
However, just because something applies Verilog, doesn't suggest it's synthesizable into your device (I'll guess you're wanting to synthesize on an FPGA or CPLD). If your device doesn't need actual gates available that will perform the logic you describe in your Verilog, you will get a synthesis error.
As Sybreon said, it's often recommended that you mentally create your logic due to the hardware resources accessible in your device, then work out how to translate that to Verilog, as opposed to just write Verilog and attempt to figure out how to adjust it to really make it synthesizable.Related articles:

  
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